The present invention relates, in general, to electronic circuits, and more particularly, to a novel recovered energy logic circuit.
In the past, a variety of circuit configurations have been utilized to reduce the amount of energy required to operate a circuit. Of particular interest are circuits referred to as recovered energy circuits. One such recovered energy logic circuit utilizes a number of bipolar transistors connected in series with alternating conductivity type, that is, PNP, NPN, PNP, etc. Each emitter is connected to a power source having an alternating waveform such as a sinusold, a triangle, or a trapezoid. The collector of each transistor is connected to the base of the following transistor and also to a capacitor that couples the collector to ground. Consequently, the collector capacitor of one transistor functions as a base or input capacitor to the following transistor.
One problem with such prior recovered energy circuits is race conditions within the circuit. During each one-half cycle, of the power source, all the transistors of one conductivity type are turned on and must discharge the capacitance on the output while simultaneously discharging the capacitance on the input. For example, during the rising portion of the power source waveform NPN transistors are turned on, and during the falling portion the PNP transistors are turned on. As a transistor turns on to charge the collector capacitor, base charge is supplied from the base or input capacitor i.e. the collector capacitor of the previous stage. If the input capacitor is discharged before the collector capacitor is completely discharged, the transistor turns off and the collector capacitor does not become fully charged. Thus, there is a race condition inherent within the circuit. Also, because of the potential drop across the base-emitter junction of a bipolar device, the input capacitor cannot be completely discharged as would be desired to provide maximum noise margin. Additionally, the switching speed of the circuit is limited. PNP transistors typically have lower switching speeds than NPN transistors. Thus, the operating frequency is limited by the switching speed of the PNP transistors.
Accordingly, it is desirable to have a recovered energy logic circuit that does not simultaneously change voltages on the input and output nodes while the circuit is active, has improved noise margin, and that has an operating frequency that is not limited by the switching rate of PNP transistors.